1. Technical Field
The present invention relates to a method for manufacturing a semiconductor device and to a semiconductor device in which an element isolation film is embedded in a silicon substrate. In particular, the invention relates to a method for manufacturing a semiconductor device and to a semiconductor device which, in the etching process of a silicon oxide film subsequent to formation of an element isolation film, can suppress a surface of the element isolation film from being etched.
2. Related Art
FIGS. 7A to 7C and 8A are sectional views for explaining a related method for manufacturing a semiconductor device. FIG. 8B is a sectional view of the semiconductor device taken along plane A-A′ in the state as shown in FIG. 8A. The semiconductor device manufactured according to the method shown by these diagrams has a first transistor located in a first element region 100c and a second transistor located in a second element region 100d. A gate insulating film 103d of the second transistor is thicker than a gate insulating film 103c of the first transistor.
First, as shown in FIG. 7A, a groove is formed in a silicon substrate 100. Next, a thermally-oxidized film 102a is formed on the side surface and the bottom surface of the groove. Further, an element isolation film 102 is embedded in the groove. The element isolation film 102 is a silicon oxide film which is formed by vapor-phase synthesis method. The element isolation film 102 separates the first element region 100c and the second element region 100d respectively from other regions. Next, the silicon substrate 100 is thermally oxidized. As a result of this, the gate insulating film 103d is formed in a second element region 100d, and a thermally-oxidized film 103a is formed in the first element region. In the state as shown in this diagram, the gate insulating film 103d does not have the necessary thickness.
Next, as shown in FIG. 7B, a resist film 150 is formed on and around the silicon substrate 100 located in the second element region, and wet etching is performed using the resist film 150 as a mask. As a result of this, the thermally-oxidized film 103a is removed. In this process, the surface of the element isolation film 2 located around the first element region is etched, and a concave section 102b is formed in the silicon substrate 100 located around the first element region (see JP-A-2002-9144 (sixth paragraph) is an example of related art).
Subsequently, as shown in FIG. 7C, the resist film 150 is removed. Next, the silicon substrate 100 is thermally oxidized. As a result of this, the gate insulating film 103c is formed in the first element region, and the thickness of the gate insulating film 103d increases to the necessary thickness.
Next, as shown in each of FIGS. 8A and 8B, a gate electrode 104c, a side wall 105c, a low-concentration impurity region 106c and an impurity region 107c which serves as source and drain of the first transistor are formed. At the same time, a gate electrode 104d, a side wall 105d, a low-concentration impurity region 106d, and an impurity region 107d which will serve as source and drain of the second transistor are formed.
As described in the example of related art, the concave section 102b is formed in the first element region. Accordingly, a section located on the concave section 102b is thinner compared to other sections in the gate insulating film 103c of the first transistor. As a result, a threshold voltage of the first transistor drops in the section located on the concave section 102b. 
In the case of a structure in which an element isolation film is embedded in a semiconductor substrate as described above, when the surface of the element isolation film is etched in the etching process of a silicon oxide film which is performed subsequent to formation of the element isolation film, a concave section located around the element isolation film is formed in the semiconductor substrate. Accordingly, a threshold voltage of a transistor drops in the section located on the concave section.